In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities, there has been and continues to be efforts toward scaling down device dimensions (e.g., at submicron levels) on semiconductor wafers. In order to accomplish such high device packing density, smaller and smaller feature and structure sizes are required in integrated circuits (ICs) fabricated on small rectangular portions of the wafer, commonly known as dies. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, the surface geometry such as corners and edges of various structures as well as the surface geometry of other features. To scale down device dimensions, more precise control of fabrication processes are required. The dimensions of and between circuit structures can be referred to as critical dimensions (CDs). Reducing CDs, and reproducing more accurate CDs facilitates achieving higher device densities through scaled down circuit structures and increased packing densities.
The process of manufacturing semiconductors or ICs typically includes more than a hundred steps (e.g., exposing, baking, developing), during which hundreds of copies of an integrated circuit may be formed on a single wafer, and more particularly on each die of a wafer. In many of these steps, material is overlayed or removed from existing layers at specific locations to form desired circuit structures or elements. Generally, the manufacturing process involves creating several patterned layers on and into a substrate that ultimately forms the complete integrated circuit. This layering process creates electrically active regions in and on the semiconductor wafer surface. The layer to layer alignment and isolation of such electrically active regions affects the precision with which structures can be formed on a wafer. If the layers are not aligned within acceptable tolerances, overlay errors can occur compromising the performance of the electrically active regions and adversely affecting chip reliability.